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HT36A0 8-Bit Music Synthesizer MCU
Features
* Operating voltage: 3.6V~5.0V * Operating frequency: 3.58MHz~12MHz * Polyphonic up to 16 notes * Independent pan and volume mix can be assigned to
(typ. 11.059MHz)
* 28 bidirectional I/O lines * Two 16-bit programmable timer/event counters with
each sound component
* Sampling rate of 44.1kHz as 11.059MHz for system
frequency
* Eight-level subroutine nesting * HALT function and wake-up feature to reduce power
overflow interrupts
* Watchdog Timer * Built-in 8-bit MCU with 2088 bits RAM * Built-in 64K16-bit ROM for program/data shared * Digital output pins for external DAC * Single data format with 16 bits digital stereo audio
consumption
* Bit manipulation instructions * 16-bit table read instructions * 63 powerful instructions * All instructions in 1 or 2 machine cycles * 48-pin SSOP package
output
* Two High D/A converter resolution: 16 bits
General Description
The HT36A0 is an 8-bit high performance RISC-like microcontroller specifically designed for music applications. It provides an 8-bit MCU and a 16 channel wavetable synthesizer. The program ROM is composed of both program control codes and wavetable voice codes, and can be easily programmed. The HT36A0 has a built-in 8-bit microprocessor which programs the synthesizer to generate the melody by setting the special register from 20H~2AH. A HALT feature is provided to reduce power consumption.
Block Diagram
VD VS VD VS S 1 6 - B it DAC 1 6 - B it DAC D DA SA
PA PB PC PD
0~ 0~ 0~ 0~
PA PB PC PD 3
7
7
7
PF0~2
6 4 K 1 6 - b it ROM 2088 RAM M u ltip lie r /P h a s e G e n e ra l
OSC1 OSC2 RES
8 - B it MCU
RCH LCH
P D 2 /L O A D
P D 3 /D C L K
P D 1 /D O U T
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HT36A0
Pin Assignment
NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 OSC1 VSS VSS VDD NC NC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 NC PB2 PB3 PB4 PB5 PB6 NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC OSC2 VDDA LCH RCH VSSA NC RES PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 NC NC PC3 PC2 PC1 PC0 PB7 NC
H T36A 0 4 8 S S O P -A
Pad Assignment
VDDA OSC1
35
OSC2
VSSA
RCH
VSS VSS VDD
38 37 36
LCH
32
34
33
31
30
PA0 PA1
2 3 4 5 6
1
29 28 27 26 25 24 7 8 9 23 22 21 11 12 13 14 15 16 17 18 19 20
RES PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4
PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1
(0 , 0 )
10
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
* The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.20 2 June 18, 2003
PB2
Chip size: 120.5 124.4 (mil)
HT36A0
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 X -1365.58 -1365.58 -1365.58 -1365.58 -1365.58 -1365.58 -1365.58 -1365.58 -1365.58 -1365.58 -1062.50 -802.90 -543.30 -283.70 -24.10 235.50 495.10 754.70 1014.30 Y 1008.20 748.60 489.00 229.40 -30.2 -289.80 -549.40 -809.00 -1068.60 -1328.20 -1415.28 -1415.28 -1415.28 -1415.28 -1415.28 -1415.28 -1415.28 -1415.28 -1415.28 Pad No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 X 1273.90 1367.30 1367.30 1367.30 1367.30 1367.30 1367.30 1367.30 1367.30 1367.30 1172.575 965.075 705.475 497.925 349.436 -328.416 -481.370 -611.375 -741.385 Y -1415.28 -1106.75 -847.15 -587.55 -327.95 -68.35 191.25 450.85 710.45 970.05 1414.78 1414.78 1414.78 1414.78 1396.935 1396.935 1368.13 1368.13 1368.13 Unit: mm
Pad Description
Pad No. 1~8 9~16 17~24 25 26 27 28 29 30 31 32 33 35 34 36, 37 38 Pad Name PA0~PA7 PB0~PB7 PC0~PC7 PD0 PD1/DOUT PD2/LOAD PD3/DCLK RES VSSA RCH LCH VDDA OSC1 OSC2 VSS VDD I/O I/O I/O I/O I/O I/O I/O I/O I 3/4 O O 3/4 I O 3/4 3/4 Internal Connection Pull-High or None Pull-High or None Pull-High or None Pull-High or None Pull-High or None Pull-High or None Pull-High or None 3/4 3/4 CMOS CMOS 3/4 3/4 3/4 3/4 Function Bidirectional 8-bit Input/Output port, wake-up by mask option Bidirectional 8-bit Input/Output port Bidirectional 8-bit Input/Output port Bidirectional 8-bit Input/Output port Bidirectional 8-bit Input/Output port DAC data out Bidirectional 8-bit Input/Output port DAC word clock Bidirectional 8-bit Input/Output port DAC bit clock Reset input, active low Negative power supply of DAC, ground R channel audio output L channel audio output DAC power supply OSC1 and OSC2 are connected to an RC network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/8 system clock. The system clock may come from the crystal, the two pins cannot be floating. Negative power supply, ground Positive power supply
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Absolute Maximum Ratings
Supply Voltage ...........................................-0.3V to 6V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-25C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD ISTB IOL IOH RPH VIH1 VIL1 VIH2 VIL2 Parameter Operating Voltage Operating Current Standby Current (WDT Disabled) I/O Ports Sink Current I/O Ports Source Current Pull-High Resistance of I/O Ports Input High Voltage for I/O Ports Input Low Voltage for I/O Ports Input High Voltage (RES) Input Low Voltage (RES) Test Conditions VDD 3/4 5V 5V 5V 5V 5V 5V 5V 5V 5V Conditions 3/4 No load fOSC=11.0592MHz No load System HALT VOL=0.5V VOH=4.5V VIL=0V 3/4 3/4 3/4 3/4 Min. 3.6 3/4 3/4 9.7 -5.2 11 3.5 0 3/4 3/4 Typ. 5 8 0 16.2 -8.7 22 3/4 3/4 4 2.5 Max. 6 16 3/4 3/4 3/4 44 5 1.5 3/4 3/4
Ta=25C Unit V mA mA mA mA kW V V V V
A.C. Characteristics
Symbol MCU interface fOSC fSYS tWDT tRES Symbol DAC interface fBC tCH tDOS tDOH tLCS tLCH DCK Bit Clock Frequency DCK Bit Clock H Level Time Data Output Setup Time Data Output Hold Time Load Clock Setup Time Load Clock Hold Time Fig 1 Fig 1 Fig 1 Fig 1 Fig 1 Fig 1 3/4 600 200 200 200 200 fSYS/16 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 MHz ns ns ns ns ns System Frequency System Clock Watchdog Time-Out Period (RC) External Reset Low Pulse Width Parameter 5V 5V 3/4 3/4 Figure 12MHz crystal 3/4 Without WDT prescaler 3/4 Min. Typ. 3/4 4 9 1 12 3/4 17 3/4 Max. 3/4 16 35 3/4 MHz MHz ms ms Unit Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
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1 /fB
C
DCK V tC
H
V
OH OL
tD
OS
tD LSB
OH
IIS
V V tL
CH
OH OL
tL
CS
LO AD V
V
OH OL
Fig 1. Audio output timing
Characteristics Curves
V vs F Characteristics Curve
H T 3 6 A 0 V v s F C h a rt
1 3 .0 1 2 .5 1 2 .0 F re q u e n c y (M H z ) 1 1 .5 1 1 .0 1 0 .5 1 0 .0 9 .5 9 .0 R =49kW R =51kW R =53kW
3 .1
3 .4
3 .7
4
4 .3
4 .6
4 .9
V o lta g e ( V )
5 .2
5 .5
H T36A 0 R
15 14 13 12 F re q u e n c y (M H z ) 11 10 9 8 7 6 5 4 43 56
v s F C h a rt
V 3 = 5 .0 V V 2 = 4 .5 V
68
75
kW
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Function Description
Execution Flow The system clock for the HT36A0 is derived from either a crystal or an RC oscillator. The oscillator frequency divided by 2 is the system clock for the MCU and it is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify a maximum of 8192 addresses for each bank. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.
S y s te m C lo c k o f M C U ( S y s te m C lo c k /2 ) PC T1 T2 T3 T4 T1
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to retrieve the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. Once a control transfer takes place, an additional dummy cycle is required. Program ROM HT36A0 provides 16 address lines WA[15:0] to read the Program ROM which is up to 1M bits, and is commonly used for the wavetable voice codes and the program memory. It provides two address types, one type is for program ROM, which is addressed by a bank pointer PF2~0 and a 13-bit program counter PC 12~0; and the
T2 T3 T4 T1 T2 T3 T4
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
Mode Initial Reset Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return From Subroutine
Program Counter *12 0 0 0 *11 0 0 0 *10 0 0 0 *9 0 0 0 *8 0 0 0 *7 0 0 0 *6 0 0 0 PC+2 *12 #12 S12 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *5 0 0 0 *4 0 0 0 *3 0 1 1 *2 0 0 1 *1 0 0 0 *0 0 0 0
Program counter Note: *12~*0: Bits of Program Counter @7~@0: Bits of PCL #12~#0: Bits of Instruction Code Rev. 1.20 6 June 18, 2003 S12~S0: Bits of Stack Register @7~@0: Bits of PCL
HT36A0
other type is for wavetable code, which is addressed by the start address ST15~0. On the program type, WA15~0= PF2~0 213+ PC12~0. On the wave table ROM type, WA15~0=ST15~0 25. Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 819216 bits, addressed by the bank pointer, program counter and table pointer. Certain locations in the program memory of each bank are reserved for special usage:
* Location 000H on bank0
0000H 0008H 000CH D e v ic e in itia liz a tio n p r o g r a m T im e r /e v e n t C o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t C o u n te r 1 in te r r u p t s u b r o u tin e P ro g ra m ROM
n00H nFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
1FFFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 0 to 1 F .
This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H on bank0.
* Location 008H
Program memory for each bank be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In this case, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon user requirements.
* Bank pointer
This area is reserved for the Timer/Event Counter 0 interrupt service program on each bank. If timer interrupt results from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H corresponding to its bank.
* Location 00CH
This area is reserved for the Timer/Event Counter 1 interrupt service program on each bank. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH corresponding to its bank.
* Table location
Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The Table Higher-order byte register (TBLH) is read only. The Table Pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must
The program memory is organized into 8 banks and each bank into 8192 16 of bits program ROM. PF[2~0] is used as the bank pointer only when PFC is configured as output mode. PFC is the control register for PF and is used to control the input/output configuration. To function as an output, the corresponding bit of the control register must be 0. After an instruction has been executed to write data to the PF register to select a different bank, note that the new bank will not be selected immediately. It is not until the following instruction has completed execution that the bank will be actually selected. It should be note that the PF register has to be cleared before setting to output mode. Table Location
Instruction(s) TABRDC [m] TABRDL [m]
*12 P12 1
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table location Note: *12~*0: Bits of table location @7~@0: Bits of table pointer P12~P8: Bits of current Program Counter
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Wavetable ROM The ST[15~0] is used to defined the start address of each sample on the wavetable and read the waveform data from the location. HT36A0 provides 21 output address lines from WA[16~0], the ST[15~0] is used to locate the major 16 bits i.e. WA[16:5] and the undefined data from WA[4~0] is always set to 00000b. So the start address of each sample have to be located at a multiple of 32. Otherwise, the sample will not be read out correctly because it has a wrong starting code. Stack Register - Stack This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). Data Memory - RAM The data memory is designed with 256 8 bits. The data memory is divided into three functional groups: special function registers, wavetable function register, and general purpose data memory (2088). Most of them are read/write, but some are read only. The special function registers include the Indirect Addressing register 0 (00H), the Memory Pointer register 0 (MP0;01H), the Indirect Addressing register 1 (02H), the Memory Pointer register 1 (MP1;03H), the Accumulator (ACC;05H), the Program Counter Lower-byte register (PCL;06H), the Table Pointer (TBLP;07H), the Table Higher-order byte register (TBLH;08H), the Watchdog Timer option Setting register (WDTS;09H), the Status register (STATUS;0AH), the Interrupt Control register (INTC;0BH), the Timer/event Counter 0 Higher-order byte register (TMR0H;0CH), the Timer/event Counter 0 Lower-order byte register (TMR0L;0DH), the Timer/event Counter 0 Control register (TMR0C;0EH), the Timer/ event Counter 1 Higher-order byte register
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH C h a n n e l n u m b e r s e le c t F r e q u e n c y n u m b e r h ig h b y te F r e q u e n c y n u m b e r lo w b y te S ta r t a d d r e s s h ig h b y te S ta r t a d d r e s s lo w R e p e a t n u m b e r lo w C o n tr o l r e g is te r L e ft v o lu m n c o n tr o l R ig h t v o lu m c o n tro l b y te b y te R e p e a t n u m b e r h ig h b y te W a v e ta b le F u n c tio n R e g is te r PF PFC ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC S p e c ia l P u r p o s e DATA M EM ORY In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1
2FH 30H G e n e ra l P u rp o s e DATA M EM ORY (2 0 8 B y te s ) :U nused. R e a d a s "0 0 "
FFH
RAM mapping (TMR1H;0FH), the Timer/event Counter 1 Lower-order byte register (TMR1L;10H), the Timer/event Counter 1 Control register (TMR1C;11H), the I/O registers (PA;12H, PB;14H, PC;16H, PD;18H), the program ROM bank select (PF;1CH)) and the I/O Control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H), and the
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program ROM bank control register (PFC;1DH). The wavetable function registers is defined between 20H~2AH. The remaining space before the 30H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 30H to FFH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through Memory pointer registers (MP0;01H, MP1;03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H directly will return the result 00H. And writing directly results in no operation. The function of data movement between two indirect addressing registers, is not supported. The memory pointer registers, MP0 and MP1, are 8-bit register which can be used to access the data memory by combining corresponding indirect addressing registers. Accumulator The accumulator closely relates to ALU operations. It is mapped to location 05H of the data memory and it can operate with immediate data. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions: Labels C Bits 0
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment & Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but can also change the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PD flags, bits in the status register can be altered by instructions like any other register. Any data written into the status register will not change the TO or PD flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. Interrupt The HT36A0 provides two internal timer/event counter interrupts on each bank. The Interrupt Control register (INTC;0BH) contains the interrupt control bits that sets the enable/disable and the interrupt request flags.
Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared by either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 STATUS register
AC Z OV PD TO 3/4
1 2 3 4 5 6~7
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Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of the INTC to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at specified locations in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and Status register (STATUS) are altered by the interrupt service program which may corrupt the desired control sequence, then the programmer must save the contents first. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC), caused by a Timer/Event Counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The Timer/Event Counter 1 interrupt is operated in the same manner as Timer/Event Counter 0. The related interrupt control bits ET1I and T1F of the Timer/Event Counter 1 are bit 3 and bit 6 of the INTC respectively. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the priorities in the following table apply. These can be masked by resetting the EMI bit. Interrupt Source Timer/event Counter 0 overflow Timer/event Counter 1 overflow Priority 1 2 Vector 08H 0CH
The Timer/Event Counter 0/1 interrupt request flag (T0F/T1F), Enable Timer/Event Counter 0/1 bit (ET0I/ET1I), Enable Master Interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, ET0I, ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T1F) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is not well controlled, once the CALL subroutine operates in the interrupt subroutine, it may damage the original control sequence.
Register
Bit No. 0 1 2 3 4 5 6 7
Label EMI 3/4 ET0I ET1I 3/4 T0F T1F 3/4
Function Controls the Master (Global) interrupt (1=enabled; 0=disabled) Unused bit, read as 0 Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Unused bit, read as 0 Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC register
INTC (0BH)
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HT36A0
Oscillator Configuration The HT36A0 provides two types of oscillator circuit for the system clock, i.e., RC oscillator and crystal oscillator. No matter what type of oscillator, the signal divided by 2 is used for the system clock. The HALT mode stops the system oscillator and ignores external signal to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 30kW to 680kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 78ms. The WDT oscillator can be disabled by mask option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock of the MCU divided by 4), determined by mask options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a period of 78ms normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with
S y s te m C lo c k /8 M ask O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
OSC1 V
DD
OSC1
OSC2 C r y s ta l O s c illa to r
fS
YS
/8
RC
OSC2
O s c illa to r
System oscillator temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, WS0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, and the programmer may use these flags to indicate some specified status. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm reset only the PC and SP are reset to zero. To clear the WDT contents (including the WDT prescaler ), 3 methods are implemented; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other set - CLR
W DT OSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog timer Rev. 1.20 11 June 18, 2003
HT36A0
WDT1 and CLR WDT2. Of these two types of instructions, only one can be active depending on the mask option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. Power Down Operation - HALT The HALT mode is initialized by a HALT instruction and results in the following...
* The system oscillator will turn off but the WDT oscilla-
is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Reset There are 3 ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
tor keeps running (If the WDT oscillator is selected). Watchdog Timer - WDT
* The contents of the on-chip RAM and registers remain
unchanged
* The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT oscillator). * All I/O ports maintain their original status.
* The PD flag is set and the TO flag is cleared. * The HALT pin will output a high level signal to disable
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that just resets the PC and SP, leaving the other circuits to maintain their state. Some registers remain unchanged during any other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different chip resets.
VDD RES S S T T im e - o u t C h ip R e s e t tS
ST
the external ROM. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. By examining the TO and PD flags, the cause for a chip reset can be determined. The PD flag is cleared when there is a system power-up or by executing the CLR WDT instruction and it is set when a HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP, the others remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may occur. If the related interrupts is disabled or the interrupts is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, a regular interrupt response takes place. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume to normal operation. In other words, a dummy cycle period will be inserted after the wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next instruction execution, this will execute immediately after a dummy period has finished. If an interrupt request flag
Reset timing chart
V
DD
RES
Reset circuit
HALT W DT W DT T im e - o u t R eset W a rm R eset
RES SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tin g C o ld R eset
OSCI
Reset configuration
Rev. 1.20
12
June 18, 2003
HT36A0
The registers status is summarized in the following table: Register Program Counter MP0 MP1 ACC TBLP TBLH WDTS STATUS INTC TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC PD PDC PF PFC CHAN FreqNH FreqNL AddrH AddrL ReH ReL ENV LVC RVC Note: Reset (Power On) 0000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- -111 ---- -111 00-- 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx xxxx xxxx xxxx * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out (Normal Operation) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --1u uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- -111 ---- -111 uu-- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu RES Reset (Normal Operation) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- -111 ---- -111 uu-- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu RES Reset (HALT) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- -111 ---- -111 uu-- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu WDT Time-out (HALT)* 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uu-u 1uuu uuuu uuuu uuuu uuuu uu-u 1uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu ---- -uuu ---- -uuu uu-- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu
Rev. 1.20
13
June 18, 2003
HT36A0
TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT buffer, and writing TMR0H will write the data and the contents of the low byte buffer into the Timer/Event Counter 0 Preload register (16-bit) simultaneously. The Timer/Event Counter 0 Preload register is changed by writing TMR0H operations and writing TMR0L will keep the Timer/Event Counter 0 Preload register unchanged. Reading TMR0H will also latch the TMR0L into the low byte buffer to avoid a false timing problem. Reading TMR0L returns the contents of the low byte buffer. In other words, the low byte of the Timer/Event Counter 0 cannot be read directly. It must read the TMR0H first to make the low byte contents of the Timer/Event Counter 0 latched into the buffer. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). The Timer/Event Counter 1 operates in the same manner as Timer/Event Counter 0. The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options. The Timer/Event Counter 1 has the same options with Timer/Event Counter 0 and is defined by TMR1C. The Timer/event Counter control registers define the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The Event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The Timer mode functions as a normal timer with the clock source coming from the instruction clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the instruction clock. In the Event count or Timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once overflow occurs, the counter is reloaded from the Timer/Event Counter Preload register and simultaneously generates the corresponding interrupt request flag (T0F/T1F; bit 5/6 of INTC). Function Unused bit, read as 0 Define the TMR active edge of Timer/Event Counter 0 (0=active on low to high; 1=active on high to low) Enable/disable timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse width measurement mode 00=Unused TMR0C/TMR1C register Rev. 1.20 14 June 18, 2003
Note: u stands for unchanged To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses during system power up or when the system awakes from a HALT state. When a system power-up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. The functional units chip reset status are shown below. Program counter Interrupt Prescaler WDT 000H Disable Clear Clear. After master reset, WDT begins counting
Timer/Event Counter (0/1) Off Input/output ports SP Timer/Event Counter Two timer/event counters are implemented in the HT36A0. The Timer/Event Counter 0 and Timer/Event Counter 1 contain 16-bit programmable count-up counters and the clock comes from the system clock divided by 4. There are three registers related to Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH). Writing TMR0L only writes the data into a low byte Label 3/4 TE TON 3/4 Bits 0~2 3 4 5 Input mode Points to the top of stack
TM0 TM1
6 7
HT36A0
In pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a transient from low to high (or high to low; if the TE bit is 0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the even if the activated transient occurs again. In other words, only one cycle measurements can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instruction. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service. In the case of timer/event counter OFF condition, writing data to the Timer/event Counter Preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMR0H/TMR1H) is read, the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer. The two timer counters of HT36A0 are internal clock mode only, so only Timer mode can be selected. Therefore the (TM1, TM0) bits can only be set to (TM1,TM0) = (1,0), and the other clock modes are invalid. Input/Output Ports There are 28 bidirectional input/output lines labeled from PA to PD, which are mapped to the data memory of [12H], [14H], [16H], [18H] respectively. All these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H or 18H). For output operation, all data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt Trigger input with or without pull-high resistor (mask option) structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The pull-high resistance will exhibit automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is 1, input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H). After a chip reset, these input/output lines remain at high levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the SET [m].i or CLR [m].i (m=12H, 14H, 16H or 18H) instruction. Some instructions first input data and then follow the output operations. For example, the SET [m].i, CLR [m].i, CPL [m] and CPLA [m] instructions read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability to wake-up the device.
S y s te m GND
C lo c k /8
D a ta B u s TM 1 TM 0 T im e r /e v e n t C o u n te r 0 P r e lo a d R e g is te r R e lo a d
TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /e v e n t C o u n te r 0 O v e r flo w T o In te rru p t
L o w B y te B u ffe r
Timer/Event Counter 0/1
Rev. 1.20
15
June 18, 2003
HT36A0
D a ta B u s D CK S Q V W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D W r ite I/O CK S Q M R e a d I/O S y s te m W a k e - U p ( P A o n ly ) M a s k O p tio n U X Q Q V
DD
DD
W eak P u ll- u p M a s k O p tio n PA PB PC PD 0~ 0~ 0~ 0~ PA PB PC PD 7 7 3 7
Input/output ports
16 Channel Wavetable Synthesizer
Wavetable Function Memory Mapping Special Register for Wavetable Synthesizer RAM 20H 21H 22H 23H 24H 25H 26H 27H 29H 2AH B7 VM BL3 FR7 ST15 ST7 WBS RE7 A_R VL7 VR7 B6 FR BL2 FR6 ST14 ST6 RE14 RE6 3/4 VL6 VR6 B5 3/4 BL1 FR5 ST13 ST5 RE13 RE5 VL9 VL5 VR5 B4 3/4 BL0 FR4 ST12 ST4 RE12 RE4 VL8 VL4 VR4 B3 CH3 FR11 FR3 ST11 ST3 RE11 RE3 ENV1 VL3 VR3 B2 CH2 FR10 FR2 ST10 ST2 RE10 RE2 ENV0 VL2 VR2 B1 CH1 FR9 FR1 ST9 ST1 RE9 RE1 VR9 VL1 VR1 B0 CH0 FR8 FR0 ST8 ST0 RE8 RE0 VR8 VL0 VR0
Wavetable Function Register Table Register Name 20H 20H 21H 21H 22H 23H 24H 25H 25H 26H 27H 27H 27H 29H 27H 2AH Register Function Channel Number Selection Change Parameter Selection Block Number Selection Frequency Number Selection Start Address Selection Waveform Format Selection Repeat Number Selection Envelope Type Selection Attach and Release Selection Left Volume Controller Right Volume Controller A_R VL9 VL7 VR7 VL6 VR6 VL5 VR5 VL8 VL4 VR4 VL3 VR3 VL2 VR2 VL1 VR9 VR1 VL0 VR8 VR0 VM BL3 FR7 ST15 ST7 WBS RE14 RE7 RE6 RE13 RE5 RE12 RE4 RE11 RE3 RE10 RE2 RE9 RE1 RE8 RE0 FR BL2 FR6 ST14 ST6 BL1 FR5 ST13 ST5 BL0 FR11 FR4 ST12 ST4 FR3 ST11 ST3 FR10 FR2 ST10 ST2 FR9 FR1 ST9 ST1 FR8 FR0 ST8 ST0 B7 B6 B5 B4 B3 CH3 B2 CH2 B1 CH1 B0 CH0
ENV1 ENV0
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16
June 18, 2003
HT36A0
* CH[3~0] channel number selection * Waveform format definition
The HT36A0 has a built-in 16 output channels and CH[3~0] is used to define which channel is selected. When this register is written to, the wavetable synthesizer will automatically output the dedicated PCM code. So this register is also used as a start playing key and it has to be written to after all the other wavetable function registers are already defined.
* Change parameter selection
The HT36A0 accepts two waveform formats to ensure a more economical data space. WBS is used to define the sample format of each PCM code.

WBS=0 means the sample format is 8-bit WBS=1 means the sample format is 12-bit
The 12-bit sample format allocates location to each sample data. Please refer to the waveform format statement as shown below.
8 - B it 1B 2B 3B 4B 5B 6B 7B 8B
These two bits, VM and FR, are used to define which register will be updated on this selected channel. There are two modes that can be selected to reduce the process of setting the register. Please refer to the statements of the following table: VM 0 0 1 FR 0 1 0 Function Update all the parameter Only update the frequency number Only update the volume
A s a m p lin g d a ta c o d e ; B m e a n s o n e d a ta b y te . 1 2 - B it 1H 1M 1L 2L 2H 2M 3H 3M 3L
A s a m p lin g d a ta c o d e N o te : " 1 H " H ig h N ib b le " 1 M " M id d le N ib b le " 1 L " L o w N ib b le
* Output frequency definition
Waveform format
* Repeat number definition
The data on BL3~0] and FR[11~0] are used to define the output speed of the PCM file, i.e. it can be used to generate the tone scale. When the FR[11:0] is 800H and BL[3:0] is 6H, each sample data of the PCM code will be sent out sequentially. When the fOSC is 12.8MHz, the formula of a tone frequency is: 50kHz FR [11 ~ 0] fOUT= fRECORD (17 - BL [3~0]) SR 2 where fOUT is the output signal frequency, fRECORD and SR is the frequency and sampling rate on the sample code, respectively. So if a voice code of C3 has been recorded which has the fRECORD of 261Hz and the SR of 11025Hz, the tone frequency (fOUT) of G3: fOUT=196Hz. Can be obtained by using the fomula: 50kHz FR[11 ~ 0] 196Hz= 261Hz 11025Hz 2 (17 - BL [3~0]) A pair of the values FR[11~0] and BL[3~0] can be determined when the fOSC is 12.8MHz.
* Start address definition
The repeat number is used to define the address which is the repeat point of the sample. When the repeat number is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80H) until the volume become close. The RE[14~0] is used to calculate the repeat address of the PCM code. The process for setting the RE[14~0] is to write the 2s complement of the repeat length to RE[14~0], with the highest carry ignored. The HT36A0 will get the repeat address by adding the RE[14~0] to the address of the end code, then jump to the address to repeat this range.
* Left and Right volume control
The HT36A0 provides two address types for extended use, one is the program ROM address which is program counter corresponding with PF value, the other is the start address of the PCM code. The ST[15~0] is used to define the start address of each PCM code and reads the waveform data from this location. The HT36A0 provides 16 input data lines from WA[15~0], the ST[15~0] is used to locate the major 16 bits i.e. WA[15~5] and the undefined data from WA[4~0] is always set as 00000b. In other words, the WA[15~0]=ST[15~0]25. So each PCM code has to be located at a multiple of 32. Otherwise, the PCM code will not be read out correctly because it has a wrong start code. Rev. 1.20 17
The HT36A0 provides the left and right volume control independently. The left and right volume are controlled by VL[9~0] and VR[9~0] respectively. The chip provides 1024 levels of controllable volume, the 000H is the maximum and 3FFH is the minimum output volume.
* Envelope type definition
The HT36A0 provides a function to easily program the envelope by setting the data of ENV[1~0] and A_R. It forms a vibrato effect by a change of the volume to attach and release alternately. The A_R signal is used to define the volume change in attach mode or release mode and ENV[1~0] is used to define which volume control bit will be changeable. On the attach mode, the control bits will be sequentially signaled down to 0. On the release mode, the control bits will be sequentially signaled up to 1. The relationship is shown in the following table.
June 18, 2003
HT36A0
A_R 0 0 0 x 1 1 1 ENV1 0 0 1 1 0 0 1 ENV0 0 1 0 1 0 1 0 Volume Control Bit VL2~0, VR2~0 VL1~0, VR1~0 VL0, VR0 No Bit VL2~0, VR2~0 VL1~0, VR1~0 VL0, VR0 Envelope type definition
* The PCM code definition
Control Bit Final Value 111b 11b 1b unchanged 000b 00b 0b
Mode
Release mode
No change mode
Attach mode
Stereo Serial Data Format The audio output data is in serial mode with 16 bit digital signal and LSB first output. There is a high sampling rate of 50kHz when the system clock is 12.8MHz and with two channel outputs for Right/Left channel. HT36A0 provides only one serial data format as IIS mode. The user could directly connect a D/A converter which can accept the IIS serial data format, like HT82V731. Mask Option No. Mask Option 1 2 3 4 5 6 WDT source CLRWDT times Wake-up Pull-High OSC mode I/O DAC pin Function On-chip RC/Instruction clock/ disable WDT One time, two times (CLR WDT1/WDT2) PA only PA, PB, PC, PD input Crystal or Resistor type PD1~3 DAC pin selection
The HT36A0 can only solve the voice format of the signed 8-bit raw PCM. And the MCU will take the voice code 80H as the end code. So each PCM code section must be ended with the end code 80H. D/A Converter Interface HT36A0 provides the IIS serial data format to support the multiple D/A converters, one bit clock output and a word clock signal for left/right stereo serial data transmission. Clock Signal The bit clock output signals DCK are used to synchronize the IIS serial data. The word clock signal LOAD divides the serial data into left channel and right channel data for two-way audio output.
* LOAD
The word clock signal LOAD is used for IIS serial data. The stereo serial data consists of 16-channel sound generator.
On IIS format, a H state on LOAD is used for the right channel, and a L state is used for the left channel.
* DCK
DCK bit clock is the clock source for the signal.
WS
R ig h t
L e ft
BCK
DATA
LSB
MSB
S a m p le O u t
D/A converter timing R vs F Characteristics curve Rev. 1.20 18 June 18, 2003
HT36A0
Application Circuit
V
DD
10W VDD VDDA PA0~PA7 PB0~PB7 PC 0~PC 7 V 100kW RES 0 .1 m F H T36A 0 V 47mF 0 .1 m F 20kW VSSA VSS 2 IN 8 VDD 1 VSS 4 5 CE 7 OUTP H T82V733 OUTN SPK 8W
DD DD
47mF
0 .1 m F
OSCI OSCO
PD 0~PD 3 LCH RCH
V re f 3 10mF
V
DD
10W VDD OSCI 12M Hz OSCO V 100kW RES 0 .1 m F H T36A 0
DD
VDDA PA0~PA7 PB0~PB7 PC 0~PC 7 PD0 P D 1 /D O U T P D 2 /L O A D P D 3 /D C L K VSSA VSS
47mF
0 .1 m F
DAC H T82V731
OP
Rev. 1.20
19
June 18, 2003
HT36A0
Package Information
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
Rev. 1.20
20
June 18, 2003
HT36A0
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 1000.1 13.0+0.5 -0.2 2.00.5 32.2+0.3 -0.2 38.20.2
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HT36A0
Carrier Tape Dimensions
D
E F W C B0
P0
P1
t
D1
P K2 A0
K1
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.1 14.20.1 2.0 Min. 1.5+0.25 4.00.1 2.00.1 12.00.1 16.200.1 2.40.1 3.20.1 0.350.05 25.5
Rev. 1.20
22
June 18, 2003
HT36A0
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
23
June 18, 2003

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